1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a dielectric material placed between semiconductor interconnect lines such that the dielectric, when deposited, forms an air gap at a midline between the interconnect lines.
2. Description of the Relevant Art
An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate. A set of interconnect lines (or conductors) which serve to electrically connect two or more components within a system is generally referred to as a xe2x80x9cbusxe2x80x9d. A collection of voltage levels are forwarded across the conductors to allow proper operation of the components. For example, a microprocessor is connected to memories and input/output devices by certain bus structures. There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses and control busses.
Conductors within a bus generally extend parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide (xe2x80x9coxidexe2x80x9d). Conductors are thereby lithography patterned across the semiconductor topography, wherein the topography comprises a substrate with a dielectric placed thereon. The topography can also include one or more layers of conductors which are sealed by an upper layer of dielectric material. Accordingly, the layers of conductors overlayed with a dielectric present a topography upon which a subsequent layer of conductors can be patterned.
Conductors are made from an electrically conductive material, a suitable material includes Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. Substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, substrate is a silicon-based material which receives p-type or n-type ions.
Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and dielectically spaced above an underlying conductor or substrate by a dielectric of thickness Td1. Each conductor is dialectically spaced from other conductors within the same level of conductors by a distance Td2. Accordingly, conductor-to-substrate capacitance CLS is determined as follows:
CLS=eWLL/Td1xe2x80x83xe2x80x83(Eq. 1)
Further, the conductor-to-conductor capacitance CLL is determined as follows:
CLL≈eTcL/Td2xe2x80x83xe2x80x83(Eq. 2)
where e is the permittivity of the dielectric material (the dielectric material between the conductor and substrate or the dielectric material between conductors), WL is the conductor width, Tc is conductor thickness, and L is the conductor length. Resistance of the conductor is calculated as follows:
R=(rL)/WLTcxe2x80x83xe2x80x83(Eq. 3)
where r represents resistivity of the conductive material, and Tc is the interconnect (conductor) thickness. Combinations of equations 1 and 3, and/or equations 2 and 3 indicate the propagation delay of a conductor as follows:
RCLS≈reL2/TcTd1
RCLL≈reL2/WLTd2
Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate. The shorter the propagation delay, the higher the speed of the circuit or circuits. It is therefore important that propagation delay be minimized as much as possible given the geometric constraints of the semiconductor topography.
Propagation delay is shown to be a function of both line-to-substrate capacitance CLS as well as line-to-line capacitance CLL. Accordingly, propagation delay is determined by parasitic capacitance values between conductors (CLL), and parasitic capacitance values between each conductor and substrate (CLS). As circuit density increases, spacing between conductors decrease and capacitance CLL becomes predominant relative to CLS. In other words, line-to-line capacitance CLL increases with decreasing spacing between conductors. FIG. 1 illustrates the effect of line-to-line spacing on CLL. As spacing decreases, CLL is shown to increase dramatically as compared to CLS. Modern integrated circuits which employ narrow interconnect spacings thereby define CLL as the primary parasitic capacitance rather than CLS.
Increases in CLL pose two major problems. First, an increase in CLL generally causes an increase in the time at which a transition on the one end of the conductor occurs at the other end. Increase in transition time (i.e., increase in speed degregation) thereby requires a longer drive period. If the conductor extends along a critical speed path, speed degregation on the line will jeopardize functionality of the overall circuit. Second, a larger CLL causes an increase in crosstalk noise. A conductor which does not transition, nonetheless receives crosstalk noise from neighboring lines which do.
It is therefore important to minimize propagation delay, especially in critical speed paths. Given the constraints of chemical compositions, it is not readily plausible to reduce the resistivity of conductor materials. Geometric constraints make it difficult to increase conductor thickness Tc or dielectric thickness Td1 or Td2. Still further, instead of reducing length L of a conductor, most modern integrated circuits employ longer interconnect lines which compound the propagation delay problems. Accordingly, a need arises for instituting a reduction in propagation delay but within the chemical and geometric constraints of existing fabrication processes. It is therefore desirable that a fabrication process be derived which can reduce propagation delays by reducing the permittivity e of dielectric material. More specifically, the desired process must be one which reduces permittivity of dielectric material between conductors since the line-to-line capacitance appears a more predominant factor than the line-to-substrate capacitance. As such, it would be desirable to employ a fabrication technique in which dielectrics between conductors achieve low permittivity.
The problems outlined above are in large part solved by a fabrication process which produces a low permittivity dielectric between interconnect lines. The process utilizes a deposition technique which purposefully allows formation of an air gap at a midline between closely spaced interconnect lines. It is known that the permittivity of air is less than that of a semiconductor dielectric, such as oxide, oxynitride, spin on polymer, etc. Accordingly, an air gap within the dielectric causes a decrease in overall permittivity between interconnects. Reduction in permittivity results in a reduction in the line-to-line capacitance CLL. Reduction in CLL is shown above to cause corresponding reduction in propagation delay RCLL. Incorporation of an air gap thereby reduces propagation delay and proves beneficial in meeting speed requirements within critical path interconnect lines, possibly interconnect lines spaced adjacent each other within a bus structure.
Broadly speaking, the present invention contemplates a dielectric interposed between a pair of integrated circuit interconnects are. The integrated circuits interconnects arranged upon a semiconductor topography. The topography includes a silicon substrate and one or more layers of dielectric and/or levels of interconnect. The dielectric includes an area therein which is void of dielectric. The voided area is deemed an air gap removed of fluid, gaseous or solid material. If any gaseous material is within the air gap, that gaseous material constitutes an inert gas. The air gap is completely encased within the dielectric near a midline between the pair of integrated circuit interconnects. The air gap area extends a spaced distance from the semiconductor topography and between the pair of interconnects. Further, the air gap area is sealed by the dielectric which flows across the upper regions of the air gap.
The present invention further contemplates a method for forming dielectric material between integrated circuit interconnects. The method includes the steps for providing a semiconductor topography and thereafter depositing a layer of metal upon the semiconductor topography. A first dielectric is then deposited upon the layer of metal, and the first dielectric and metal layers are thereafter removed in select regions across the semiconductor topography. Select removal of the first dielectric and the metal allows formation of a spaced set of first dielectric-covered interconnects. A second dielectric material is then deposited from a silane source upon the spaced set of first dielectric-covered interconnects to form an air gap between the dielectric-covered interconnects.
The first and second dielectric materials are preferably deposited from a chemical vapor deposition chamber maintained substantially near or slightly below atmospheric pressure. In order to achieve an air gap during second dielectric deposition, the cumulative thickness of the metal and the first dielectric is maintained greater than a distance between the spaced set of first dielectric-covered interconnects. First dielectric thickness is thereby necessary to ensure an aspect ratio (i.e., spacing height versus spacing width) greater than 1.0 by ensuring the cumulative thickness of metal and first dielectric (spacing height) is greater than a distance between the spaced set of dielectric-covered interconnects. Depositing the second dielectric from an atmospheric pressure chemical vapor deposition (APCVD) chamber upon the area of controlled aspect ratio thereby allows formation of voids or air gaps in the regions of interest.